1. Technical Field of the Invention
The present invention relates to testing a ferroelectric memory device, and particularly to performing a stress test on a ferroelectric memory device.
2. Description of the Related Art
Ferroelectricity is a phenomenon which can be observed in a relatively small class of dielectrics called ferroelectric materials. In a normal dielectric, upon the application of an electric field, positive and negative charges will be displaced from their original positionxe2x80x94a concept which is characterized by the dipole moment or polarization. This polarization or displacement will vanish, however, when the electric field returns back to zero. In a ferroelectric material, on the other hand, there is a spontaneous polarizationxe2x80x94a displacement which is inherent to the crystal structure of the material and does not disappear in the absence of the electric field. In addition, the direction of this polarization can be reversed or reoriented by applying an appropriate electric field.
These characteristics result in ferroelectric capacitors, formed from ferroelectric film or material disposed between parallel conduction plates, being capable of storing in a nonvolatile manner a first charge corresponding to a first polarization state in which the direction of polarization is in a first direction, and a second charge corresponding to a second polarization state in which the direction of polarization is in a second direction opposite the first direction. Ferroelectric capacitors are utilized in nonvolatile random access memory devices having a memory cell array architecture that is similar to the memory cell array architecture of dynamic random access memory (DRAM) devices.
In general terms, there are two types of ferroelectric memory cells. Referring to FIG. 1A, a one transistor, one capacitor (1T1C) memory cell utilizes a pass gate transistor T connected between a column line B and a first plate of ferroelectric capacitor C. A second plate of ferroelectric capacitor C is connected to a plate line P. The gate terminal of pass gate transistor T is connected to a word line W. A memory device utilizing a 1T1C memory cell uses a reference memory cell that is accessed at the same time the 1T1C memory cell is accessed so as to provide a charge differential appearing across a pair of column lines coupled to the 1T1C cell and the reference cell. The use of 1T1C ferroelectric memory cells is known in the art.
Referring to FIG. 1B, a two transistor, two capacitor (2T2C) memory cell includes two ferroelectric capacitors C1 and C2. A first pass gate transistor T1 is connected between a first plate of ferroelectric capacitor C1 and a first column line BL of a column line pair. A second pass gate transistor T2 is connected between a first plate of ferroelectric capacitor C2 and a second column line BLxe2x80x2 of the column line pair. A second plate of ferroelectric capacitors C1 and C2 is connected to a plate line P. The gate terminal of pass gate transistors T1 and T2 is connected to the word line W. Each capacitor C1 and C2 stores a charge representative of the polarization state thereof, the charge combining with the charge of the other capacitor to result in a charge differential appearing across column lines BL and BLxe2x80x2 when the 2T2C memory cell is accessed. The polarity of the charge differential denotes the binary value stored by the 2T2C memory cell. The use of 2T2C ferroelectric memory cells is known in the art.
A problem with ferroelectric memory devices is the existence of a phenomenon known as imprint. Imprint is a characteristic of ferroelectric films that refers to the tendency of a ferroelectric film/capacitor to prefer one polarization state over another polarization state. Imprint is known to occur when a ferroelectric capacitor is maintained in a single polarization state for a prolonged period of time. Imprint adversely effects the ability of a ferroelectric capacitor to switch between the polarization states. Consequently, the existence of imprint may directly impact the performance of a ferroelectric memory device.
The performance of ferroelectric memory cells has been seen to degrade over time due to a number of other phenomena as well. For instance, ferroelectric memory cells may be effected by fatigue, retaining data over time, etc. When holding data over a prolonged period of time, such as under accelerated conditions during burn-in, a ferroelectric memory cell may be seen to degrade over the course of several hours or days. FIG. 2 shows how a ferroelectric memory cell may be degraded, with the polarization characteristic being shown for a normal ferroelectric memory cell in continuous set of lines and the polarization characteristic being shown for a degraded ferroelectric memory cell in dashed lines.
Often, integrated circuits are tested both before and after packaging to detect latent defects. One aspect of this testing procedure is referred to as xe2x80x9cstress testing.xe2x80x9d Stress testing of integrated circuits, such as memory devices, is typically accomplished by applying an overvoltage to the gates of the transistors in the memory array. For example, testing on a memory device rated at five volts may be performed at nine volts. To perform this test, it is common to activate multiple wordlines and columns on a simultaneous basis thus applying the testing overvoltage at each memory cell within the memory array. Defective columns and rows may then be detected. The defective portions of the device are then replaced using built-in redundancy features, or the device is discarded as defective.
Based upon the foregoing, there is a need for a circuit and method for effectively performing a stress test on a ferroelectric memory device.
Embodiments of the present invention overcome shortcomings in testing ferroelectric memory devices and satisfy a significant need for suitably performing a stress test on the ferroelectric memory device. In accordance with an embodiment of the present invention, a ferroelectric memory device includes a memory array of memory cells organized into rows and columns, with each row of memory cells being coupled to a word line and a plate line and each column of memory cells being coupled to a bit line. The ferroelectric memory device further includes address decode circuitry for receiving an address value and asserting a signal appearing on at least one row line to connect at least one row of memory cells to the column lines. In addition, the ferroelectric memory device includes test circuitry for receiving at least one test control signal and in response to the at least one test control signal allowing a voltage differential to be applied between the column lines and the plate lines, so that a stress voltage may be applied across the ferroelectric capacitor of each of the memory cells.
The operation of the ferroelectric memory device in performing a stress test includes connecting each row of memory cells to the column lines and applying a stress voltage between the column lines and the plate lines for a predetermined period of time. In this way, the dielectric material of the capacitor of each memory cell is stressed at elevated voltages for detecting weak oxides, thin oxides, particle defects, etc. in the memory cells.